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general description the max17595/max17596/max17597 is a family of peak- current-mode controllers for design of wide input-voltage flyback and boost regulators. the max17595 offers optimized input thresholds for universal input ac-dc converters and telecom dc-dc (36v to 72v input range) power supplies. the max17596/max17597 offer input thresholds suitable for low-voltage dc-dc applications (4.5v to 36v). the max17597 implements a boost con - verter. all three controllers contain a built-in gate driver for external n-channel mosfets. the max17595/max17596/max17597 house an internal error amplifier with 1% accurate ref - erence, eliminating the need for an external reference. the switching frequency is programmable from 100khz to 1mhz with an accuracy of 8% , allowing optimization of magnetic and filter components, result - ing in compact and cost-effective power conversion. for emi-sensitive applications, the max17595/max17596/ max17597 family incorporates a programmable frequen - cy dithering scheme, enabling low-emi spread-spectrum operation. users can start the power supply precisely at the desired input voltage, implement input overvoltage protection, and program soft-start time. a programmable slope com - pensation scheme is provided to ensuree stability of the peak-current-mode control scheme. hiccup-mode overcurrent protection and thermal shutdown are provided to minimize dissipation in overcurrent and overtemperature fault conditions. applications universal input offline ac-dc power supplies wide-range dc-input flyback/boost battery chargers battery-powered applications industrial, telecom, and automotive applications benefits and features s peak-current-mode offline (universal input ac) and telecom (36v to 72v) flyback controller max17595 s peak-current-mode dc-dc (4.5v to 36v) flyback controllermax17596 s peak-current-mode nonsynchronous (4.5v to 36v) boost pwm controllermax17597 s current mode control provides excellent transient response s low 20a startup supply current s 100khz to 1mhz programmable switching frequency with optional synchronization s programmable frequency dithering for low-emi spread-spectrum operation s adjustable current limit with external current- sense resistor s fast cycle-by-cycle peak current limiting s hiccup-mode short-circuit protection s overtemperature protection s programmable soft-start and slope compensation s input overvoltage protection s space-saving, 3mm x 3mm tqfn package 19-6178; rev 1; 2/13 ordering information/selector guide appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max17595.related . max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 v in to sgnd .......................................................... -0.3v to +40v v drv to sgnd .................................. -0.3v to +16v (max17595) v drv to sgnd .......... -0.3v to +6v (max17596 and max17597) ndrv to sgnd .................................... -0.3v to +(v drv + 0.3)v en/uvlo to sgnd .................................. -0.3v to +(v in + 0.3)v ovi, rt, dither, comp, ss, fb, slope to sgnd .................................................... -0.3v to +6v cs to sgnd ............................................................ -0.8v to +6v pgnd to sgnd .................................................... -0.3v to +0.3v maximum input/output current (continuous) v in , v drv .......................................................................... 100ma ndrv (pulsed, for less than 100ns) .......................... 1.5a/-0.9a continuous power dissipation tqfn (single-layer board) (derate 20.8mw/ n c above +70 n c) ............................ 1666mw operating temperature range ........................ -40 n c to +125 n c storage temperature range ............................ -65 n c to +150 n c junction temperature ..................................................... +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v in = 12v (for the max17595, bring v in up to 21v for startup), v cs = v slope = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en/uvlo = +2v; ndrv, ss, comp are unconnected, r rt = 25k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) junction-to-ambient thermal resistance ( q ja ) .............. 48c/w junction-to-case thermal resistance ( q jc ) ..................... 7c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units input supply (v in ) v in voltage range v in max17595 8 29 v max17596/max17597 4.5 36 v in bootstrap uvlo wakeup v in-uvr v in rising # max17595 18.5 20 21.5 v max17596/max17597 3.8 4.1 4.4 v in bootstrap uvlo shutdown level v in-uvf v in falling $ max17595 6.5 7 7.5 v max17596/max17597 3.6 3.9 4.2 v in supply startup current (under uvlo) i vin- startup v in < uvlo 20 32 f a v in supply shutdown current i in-sh v en = 0v 20 32 f a v in supply current i in-sw switching, f sw = 400khz 2 ma v in clamp voltage v inc max17595, i vin = 2ma sinking, v en = 0v (note 3) 30 33 36 v enable (en) en undervoltage threshold v enr v en rising # 1.16 1.21 1.26 v v enf v en falling $ 1.1 1.15 1.2 en input leakage current i en v en = 1.5v, t a = +25 n c -100 +100 na max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
3 electrical characteristics (continued) (v in = 12v (for the max17595, bring v in up to 21v for startup), v cs = v slope = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en/uvlo = +2v; ndrv, ss, comp are unconnected, r rt = 25k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) parameter symbol conditions min typ max units internal ldo (v drv ) v drv output voltage range v drv 8v < v in < 15v and 0ma < i vdrv < 50ma (max17595) 7.1 7.4 7.7 v 6v < v in < 15v and 0ma < i vdrv < 50ma (max17596/max17597) 4.7 4.9 5.1 v drv current limit i vdrv-max 70 100 ma v drv dropout v vdrv-do v in = 4.5v, i vdrv = 20ma (max17596/ max17597) 4.2 v overvoltage protection (ovi) ovi overvoltage threshold v ovir v ovi rising # 1.16 1.21 1.26 v v ovif v ovi falling $ 1.1 1.15 1.2 ovi masking delay t ovi-md 2 f s ovi input leakage current i ovi v ovi = 1v, t a = +25 n c -100 +100 na oscillator (rt) ndrv switching frequency range f sw 100 1000 khz ndrv switching frequency accuracy -8 +8 % maximum duty cycle d max f sw = 400khz (max17595/max17596) 46 48 50 % (max17597) 90 92.5 95 synchronization (dither/sync) synchronization logic-high input v hi-sync 3 v synchronization pulse width 50 ns synchronization frequency range f sync (max17595/max17596) (note 4) 1.1 x f sw 1.8 x f sw hz dithering ramp generator (dither/sync) charging current 45 50 55 f a discharging current 43 50 57 f a ramp-high trip point 2 v ramp-low trip point 0.4 v max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
4 electrical characteristics (continued) (v in = 12v (for the max17595, bring v in up to 21v for startup), v cs = v slope = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en/uvlo = +2v; ndrv, ss, comp are unconnected, r rt = 25k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) parameter symbol conditions min typ max units soft-start (ss) soft-start charging current i ssch 9 10 11 f a ss bias voltage v ss 1.19 1.21 1.23 v ndrv driver (ndrv) pulldown impedance r ndrv-n i ndrv (sinking) = 100ma 1.37 3 i pullup impedance r ndrv-p i ndrv (sourcing) = 50ma 4.26 8.5 i peak sink current c ndrv = 10nf 1.5 a peak source current c ndrv = 10nf 0.9 a fall time t ndrv-f c ndrv = 1nf 10 ns rise time t ndrv-r c ndrv = 1nf 20 ns current-limit comparator (cs) cycle-by-cycle peak current-limit threshold v cs-peak 290 305 320 mv cycle-by-cycle runaway current-limit threshold v cs-run 340 360 380 mv current-sense leading- edge blanking time t cs-blank from ndrv rising # edge 70 ns propagation delay from comparator input to ndrv t pdcs from cs rising (10mv overdrive) to ndrv falling (excluding leading edge blanking) 40 ns number of consecutive peak- current-limit events to hiccup n hiccup-p 8 events number of runaway- current-limit events to hiccup n hiccup-r 1 event overcurrent hiccup timeout 32,768 cycle minimum on-time t on-min 90 130 170 ns slope compensation (slope) slope bias current i slope 9 10 11 f a slope resistor range 25 200 k i max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
5 electrical characteristics (continued) (v in = 12v (for the max17595, bring v in up to 21v for startup), v cs = v slope = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en/uvlo = +2v; ndrv, ss, comp are unconnected, r rt = 25k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) note 2: all devices 100% production tested at t a = +25c. limits over temperature are guaranteed by design. note 3: the max17595 is intended for use in universal input power supplies. the internal clamp circuit at v in is used to prevent the bootstrap capacitor from charging to a voltage beyond the absolute maximum rating of the device when en is low (shutdown mode). externally limit the maximum current to v in (hence to clamp) to 2ma (max) when en is low. note 4: using an external clock for synchronization increases the maximum duty cycle by a factor equal to f sync / f sw for the max17595/max17596. external synchronization is not available for the max17597. parameter symbol conditions min typ max units slope voltage range for default slope compensation 4 v slope voltage range for programmable slope compensation 0.2 2 v slope compensation ramp r slope = 100k w 140 165 190 mv/ f s default slope compensation ramp 4v < v slope 50 mv/ f s pwm comparator comparator offset voltage v pwm-os v comp , when v cs = 0 1.65 1.81 2 v current-sense gain a cs-pwm d v comp / d v cs 1.75 1.97 2.15 v/v comparator propagation delay t pwm change in v cs = 10mv (including internal lead- edge blanking) 110 ns error amplifier fb reference voltage v ref v fb , when i comp = 0 and v comp = 1.8v 1.19 1.21 1.23 v fb input bias current i fb v fb = 1.5v, t a = +25 n c -100 +100 na voltage gain a eamp 90 db transconductance gm 1.5 1.8 2.1 ms transconductance bandwidth bw open-loop (gain = 1), -3db frequency 10 mhz source current v comp = 1.8v, v fb = 1v 80 120 210 f a sink current v comp = 1.8v, v fb = 1.75v 80 120 210 f a thermal shutdown thermal-shutdown threshold temperature rising +160 n c thermal-shutdown hysteresis 20 n c max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
6 typical operating characteristics (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) bootstrap uvlo wake-up level vs. temperature (max17595) max17595/6/7 toc01 temperature (c) bootstrap uvlo wake-up level (v) 20 40 60 80 100 120 0 -20 19.99 20.00 20.01 20.02 20.03 20.04 19.98 -40 v in falling threshold vs. temperature (max17596 / max17597) max17595/6/7 toc04 temperature (c) v in uvlo shutdown threshold (v) 20 40 60 80 100 120 0 -20 3.92 3.97 -40 3.88 3.89 3.90 3.91 en / uvlo falling threshold vs. temperature max17595/6/7 toc06 temperature (c) en / uvlo falling threshold (v) 20 40 60 80 100 120 0 -20 1.149 1.145 -40 1.146 1.147 1.148 en / uvlo rising threshold vs. temperature max17595/6/7 toc05 temperature (c) en / uvlo rising threshold (v) 20 40 60 80 100 120 0 -20 1.209 1.202 -40 1.203 1.204 1.205 1.206 1.207 1.208 ovi rising threshold vs. temperature max17595/6/7 toc07 temperature (c) ovi rising threshold (v) 20 40 60 80 100 120 0 -20 1.211 1.207 -40 1.208 1.209 1.210 v in wake-up level vs. temperature (max17596 / max17597) max17595/6/7 toc02 temperature (c) v in wake-up level (v) 20 40 60 80 100 120 0 -20 4.13 4.07 -40 4.08 4.09 4.11 4.10 4.12 v in falling threshold vs. temperature (max17595) max17595/6/7 toc03 temperature (c) v in bootstrap uvlo shutdown level (v) 20 40 60 80 100 120 0 -20 7.000 7.005 7.010 7.015 7.020 7.025 6.995 -40 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
7 typical operating characteristics (continued) (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) ovi falling threshold vs. temperature max17595/6/7 toc08 temperature (c) ovi falling threshold (v) 20 40 60 80 100 120 0 -20 1.1480 1.1485 1.1490 1.1495 1.1500 1.1505 1.1475 -40 ndrv switching frequency vs. resistor max17595/6/7 toc11 frequency selection resistor (k i ) ndrv switching frequency (khz) 1000 0 51 52 53 54 55 56 57 58 59 5 100 200 300 400 600 700 800 900 500 frequency dithering vs. r dither r dither (k i ) frequency dithering (%) 900 800 700 600 500 400 300 4 6 8 10 12 14 2 200 1000 max17595/6/7 toc13 ndrv switching frequency vs. temperature max17595/6/7 toc12 temperature (c) ndrv switching frequency (khz) 20 40 60 80 100 120 0 -20 950 850 750 650 550 450 350 250 150 50 -40 r rt = 10ki r rt = 100ki switching waveforms (max17595) max17595/6/7 toc14 i pri 1a /div 4s / div v drain 100v/div v in supply current under uvlo vs. temperature max17595/6/7 toc09 temperature (c) v in supply current under uvlo (a) 20 40 60 80 100 120 0 -20 20.5 21.5 22.5 23.5 24.5 25.5 19.5 -40 switching current vs. temperature max17595/6/7 toc10 temperature (c) switching current (ma) 20 40 60 80 100 120 0 -20 2.5 1.5 -40 1.6 1.7 1.8 1.9 2.1 2.2 2.3 2.4 2.0 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
8 typical operating characteristics (continued) (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) enable startup max17595/6/7 toc15 comp 1v/div 2ms / div v out 10v/div en / uvlo 5v/div switching current vs. switching frequency switching frequency (hz) switching current (ma) 900 800 700 500 600 400 300 200 1.7 1.9 2.1 2.3 2.5 1.5 100 1000 max17595/6/7 toc18 bode plot (figure 9 output) max17595/6/7 toc20 phase 36/div gain 10db/div bandwidth = 11.5khz phase margin = 50.9 66 82 2 44 18 1 load transient response (figure 9 output) max17595/6/7 toc19 0.4ms / div v out (ac) 0.5v/div i load 0.5a /div load current (a) 0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 efficiency graph (figure 9 output) efficiency (%) 10 20 30 40 60 70 80 90 100 0 50 max17595/6/7 toc21 v dc = 120v enable shutdown max17595/6/7 toc16 comp 1v/div 400s / div v out 10v/div en / uvlo 5v/div hiccup operation max17595/6/7 toc17 1ms / div v out 10v/div v drain 100v/div i pri 2a /div max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
9 pin description pin configuration pin name function 1, 12 n.c. no connection 2 slope slope compensation input. a resistor, r slope , connected from slope to sgnd programs the amount of slope compensation with reference-voltage soft-start mode. connecting this pin to sgnd enables duty-cycle soft-start with default slope compensation of 50mv/ f s. setting v slope > 4v enables reference voltage soft-start with default slope compensation of 50mv/ f s. 3 rt switching frequency programming resistor connection. connect resistor r rt from rt to sgnd to set the pwm switching frequency. 4 dither/sync frequency dithering programming or synchronization connection. for spread-spectrum frequency operation, connect a capacitor from dither to sgnd, and a resistor from dither to rt. to synchronize the internal oscillator to the externally applied frequency (max17595/max17596 only), connect dither/sync to the synchronization pulse. 5 comp transconductance amplifier output. connect the frequency compensation network between comp and sgnd. 6 fb transconductance amplifier inverting input 7 ss soft-start capacitor pin for flyback regulator. connect a capacitor c ss from ss to sgnd to set the soft-start time interval. 8 sgnd signal ground. connect sgnd to the signal ground plane. 9 cs current-sense input. peak-current-limit trip voltage is 300mv (typ). 10 pgnd power ground. connect pgnd to the power ground plane. 11 ndrv external switching nmos gate-driver output 15 16 14 13 5 6 7 rt dither / sync 8 n.c. pgnd cs n.c. 13 v in 4 12 10 9 en / uvlo ovi ep sgnd ss fb comp slope ndrv 2 11 v drv tqfn max17595 max17596 top view + 15 16 14 13 5 6 7 rt dither 8 n.c. pgnd cs n.c. 13 v in 4 12 10 9 en /u vlo ovi ep sgnd ss fb comp slope ndrv 2 11 v drv tqfn max17597 + max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
10 pin description (continued) detailed description the max17595 offers a bootstrap uvlo wake-up level of 20v with a wide hysteresis, and is optimized for imple - menting isolated and nonisolated universal (85v to 265v ac) offline single-switch flyback converter or telecom (36v to 72v) power supplies. the max17596/max17597 offer a uvlo wake-up level of 4.4v and are well-suited for low-voltage dc-dc flyback/boost power supplies. an internal 1% reference (1.21v) can be used to regulate the output in nonisolated flyback and boost applications. additional semiregulated outputs, if needed, can be gen - erated by using additional secondary windings on the flyback converter transformer. the max17595/max17596/max17597 family utilizes peak-current-mode control and external compensation for optimizing closed-loop performance. the devices include cycle-by-cycle peak current limit, and eight consecutive occurrences of current-limit-event trigger hiccup mode, which protects external components by halting switching for a period of 32,768 cycles. . input voltage range ( v in ) the max17595 has no limitation on maxi - mum input voltage, as long as the external components are rated suitably and the maximum operating voltages of the max17595 are respected. the max17595 implements a rising and falling uvlo threshold that allows it to be successfully used in univer - sal input (85v to 265v ac) rectified bus applications, in rectified 3-phase dc bus applications, and in telecom (36v to 72v dc) applications. the max17596/max17597 are intended to implement flyback (isolated and nonisolated) and boost convert - ers. the v in pin of the max17596/max17597 has a maximum operating voltage of 36v. the max17596/ max17597 implement rising and falling thresholds on the v in pin that assume power-supply startup schemes typical of low-voltage dc-dc applications, down to an input voltage of 4.5v dc. therefore, flyback /boost converters with a 4.5v to 36v supply voltage range can be implemented with the max17596/max17597. internal linear regulator (v drv ) the internal functions and driver circuits are designed to operate from 7.4v (max17595) or 5v (max17596/ max17597) power-supply voltages. the max17595/ max17596/max17597 family has an internal linear regu - lator that is powered from the v in pin. the output of the linear regulator is connected to the v drv pin, and should be decoupled with a 1 f f capacitor to ground for stable operation. the v drv regulator output supplies all the oper - ating current of the max17595/max17596/max17597. the maximum operating voltage on the v in pin is 29v for the max17595, and 36v for the max17596/max17597. pin name function 13 v drv linear regulator output and driver input. connect a 1f bypass capacitor from v drv to sgnd as close as possible to the ic. 14 v in internal v drv regulator input. connect v in to the input voltage source. bypass v in to pgnd with a 1 f f minimum ceramic capacitor. 15 en/uvlo enable/undervoltage lockout. to externally program the uvlo threshold of the input supply, connect a resistive divider between input supply, en, and sgnd. 16 ovi overvoltage comparator input. connect a resistive divider between the input supply, ovi, and sgnd to set the input overvoltage threshold. ep exposed pad max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
11 figure 1. max17595/max17596/max17597 block diagram (*see note 4.) control and driver logic hiccup 8 peak events or 1 runaway ssdone ss ss ssdone 1.21v chippen dither/ sync 1.21v 1.21v uvlo v drv dither/sync ndrv pgnd cs slope comp fb v in en / uvlo ovi rt ss sgnd 7.4v (max17595) or 5v (max17596/ max17597) osc peaklim comp 305mv 360mv fixed or var 10a 10a 50a runaway comp pwm comp osc osc 70ns blanking r r internal reference 1.21v 1x driver v drv 2v/ 0.4v pgnd slope decode 0.9v 5v ldo pok max17595 max17596 max17597* 7.4v ldo thermal sensor chipen max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
12 n-channel mosfet gate driver (ndrv) the devices offer a built-in gate driver for driving an external n-channel mosfet. the ndrv pin can source/ sink peak currents in excess of 900ma /1500ma. maximum duty cycle the max17595/max17596 operate at a maximum duty cycle of 49%. the max17597 offers a maximum duty cycle of 94% to implement flyback and boost converters involving large input-to-output voltage ratios in dc-dc applications. slope compensation is necessary for sta - ble operation of peak-current-mode controlled convert - ers such as the max17595/max17596 /max17597, in addition to the loop compensation required for small signal stability. the max17595/max17596/max17597 implement a slope pin for this purpose. see the slope compensation section for more details. soft-start (ss) the devices implement soft-start operation for the fly - back/boost regulators. a capacitor connected to the ss pin programs the soft-start period. the soft-start feature reduces input inrush current during startup. when the voltage on the slope pin is more than 0.2v, the refer - ence to the internal error amplifier is ramped up from 0v to 1.21v in a linear manner, as programmed by the soft-start capacitor. see the programming soft-start (ss) (ss ) section. switching frequency selection (rt) the ics switching frequency is programmable between 100khz and 1mhz with resistor r rt connected between rt and sgnd. use the following formula to determine the appropriate value of r rt needed to generate the desired output-switching frequency (f sw ): = 10 rt sw 10 r f where f sw is the desired switching frequency. frequency dithering for spread-spectrum applications (low emi) the switching frequency of the converter can be dithered in a range of q 10% by connecting a capaci - tor from dither/sync to sgnd, and a resistor from dither to rt. spread-spectrum modulation technique spreads the energy of switching frequency and its har - monics over a wider band while reducing their peaks, helping to meet stringent emi goals. applications information startup voltage and input overvoltage protection setting (en /uvlo, ovi) the devices en/uvlo pin serves as an enable/disable input, as well as an accurate programmable input uvlo pin. the devices do not commence startup operation unless the en/uvlo pin voltage exceeds 1.21v (typ). the devices turn off if the en/uvlo pin voltage falls below 1.15v (typ). a resistor-divider from the input dc bus to ground can be used to divide down and apply a fraction of the input dc voltage (v dc ) to the en/uvlo pin. the values of the resistor-divider can be selected so the en/uvlo pin voltage exceeds the 1.23v (typ) turn- on threshold at the desired input dc bus voltage. the same resistor-divider can be modified with an additional resistor (r ovi ) to implement input overvoltage protec - tion in addition to the en/uvlo functionality as shown in figure 2 . when voltage at the ovi pin exceeds 1.21v (typ), the devices stop switching and resume switching opera tions only if voltage at the ovi pin falls below 1.15v (typ). for given values of startup dc input voltage (v start ) and input overvoltage-protection voltage (v ovi ), the resistor values for the divider can be calculated as fol lows, assuming a 24.9k i resistor for r ovi : ovi en ovi start v r r 1k v ?? =? ?? ?? i where r ovi is in k i , while v start and v ovi are in volts. start sum ovi en v r r r 1k 1.21 ?? = + ? ?? ?? ?? ?? i where r en and r ovi are in k i , while v start is in volts. in universal ac input applications, r sum may need to be implemented as equal resistors in series (r dc1 , r dc2 , and r dc ) so that voltage across each resistor is limited to its maximum operation voltage. = = = sum dc1 dc2 dc3 r rr r k 3 i for low-voltage dc-dc applications based on the max17596/max17597, a single resistor can be used in the place of r sum , as the voltage across it is approxi - mately 40v. max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
13 figure 2. programming en /uvlo and ovi startup operation the max17595 is optimized for implementing an offline single-switch flyback converter and has a 20v v in uvlo wake-up level with hysteresis of 15v (min). in offline applications, a simple cost-effective rc startup circuit is used. when the input dc voltage is applied, the startup resistor (r start ) charges the startup capacitor (c start ), causing the voltage at the v in pin to increase towards the wake-up v in uvlo threshold (20v typ). during this time, the max17595 draws a low startup current of 20 f a (typ) through r start . when the voltage at v in reaches the wake-up v in uvlo threshold, the max17595 commenc - es switching and control operations. in this condition, the max17595 draws 2ma (typ) current from c start for its internal operation. in addition, the gate-drive current is also drawn from c start , which is a function of the gate charge of the external mosfet used and switching fre - quency. since this total current cannot be supported by the current through r start , the voltage on c start starts to drop. when suitably configured, as shown in figure 3 , the external mosfet is switched by the ndrv pin and the flyback converter generates pulses on bias winding nb. the soft-start period of the con - verter should be programmed so the bias winding pulses sustain the voltage on c start before it falls below 7v, thus allowing continued operation. the large hysteresis of the max17595 allows for a small startup capacitor (c start ). the low startup current (20 f a typ) allows the use of a large startup resistor (r start ), thus reducing power dissipation at higher dc bus voltages. r start might need to be implemented as equal, multiple resistors in series (r in1 , r in2 , and r in3 ) to share the applied high dc voltage in offline applications so that the voltage across each resistor is limited to its maximum continuous operating voltage rating. r start and c start can be calculated as: + ?? ?? = ?? + ?? ?? vdrv in ss start ss g sw 6 c i t 0.1 c 0.75 f t qf 0.04 10 where i in is the supply current drawn at the v in pin in ma, q g is the gate charge of the external mosfet used in nc, f sw is the switching frequency of the converter in hz, and t ss is the soft-start time programmed for the fly - back converter in ms. c vdrv is a cummulative capacitor used in v drv node in f. see the programming soft-start of flyback/boost converter (ss) section. ( ) start start start v 10 50 rk 1c ? = + ?? ?? i where c start is the startup capacitor in f f. for designs that cannot accept power dissipation in the startup resistors at high dc input voltages in offline appli- cations, the startup circuit can be set up with a current source instead of a startup resistor as shown in figure 4 . the startup capacitor (c start ) can be calculated using the above equation: resistors r sum and r isrc can be calculated as: start sum beq1 isrc v rm 10 v rm 70 = w = w the v in uvlo wake-up threshold of the max17596/ max17597 is set to 4.1v (typ) with a 200mv hyster esis, optimized for low-voltage dc-dc applications down to 4.5v. for applications where the input dc voltage is low enough (e.g., 4.5v to 5.5v dc) that the power loss incurred to supply the operating current of the max17596/ max17597 can be tolerated, the v in pin is directly connected to the dc input, as shown in figure 5 . in the case of higher dc input voltages (e.g., 16v to 32v dc), a startup circuit, such as that shown in figure 6 , can be used to minimize power dissipation. in this startup ovi r dc1 r sum r dc2 r dc3 en / uvlo r en r ovi max17595 max17596 max17597 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
14 scheme, the transistor (q1) supplies the switching cur - rent until a bias winding nb comes up and turns off q1. the resistor (r z ) can be calculated as: ? = w z inmin r 2 (v 6.3) k programming soft-start (ss) the soft-start period for the devices can be programmed by selecting the value of the capacitor c ss connected from the ss pin to sgnd. capacitor c ss can be calcu - lated as: ss ss c 8.2645 t nf = where t ss is expressed in ms. this equation is directly applicable to the boost converter application circuit of figure 11. for optoisolated converters, the soft-start period is approximately equal to 30% of t ss when the figure 3. max17595 rc-based startup circuit figure 4. max17595 current-source-based startup circuit v drv v dc c out v in v out c vdrv c start ldo drv cs ndrv d1 d2 ns np nb max17595 v dc r in1 r start r in2 r in3 r in1 v dc r sum r in2 v drv v dc c out d1 v in r isrc v out c vdrv r s c start r in3 ldo drv cs ndrv d2 ns np nb max17595 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
15 error amplifier is set up as a proportional gain amplifier as shown in figure 9 . programming output voltage the devices incorporate an error amplifier with a 1% pre - cision voltage reference that enables negative feedback control of the output voltage. the output voltage of the switching converter can be programmed by selecting the values for the resistor-divider connected from v out , and the flyback /boost output to ground, with the midpoint of the divider connected to the fb pin ( figure 7 ). with r b selected in the 20k i to 50k i range, r u can be calcu - lated as: out ub b v r r 1 k , where r is in k . 1.21 ?? =? ?? ?? ii peak-current-limit setting (cs) the d evices include a robust overcurrent protection scheme that protects the device under overload and short-circuit conditions. a current-sense resistor, connected between the source of the mosfet and pgnd, sets the peak current limit. the current-limit comparator has a voltage figure 6. max17596/max17597 typical startup circuit with bias winding to turn off q1 and reduce power dissipation figure 5. max17596/max17597 typical startup circuit with v in connected directly to dc input v drv v dc c out c drv np ns d1 v in v in v out r s cs ndrv ldo max17596 max17597 drv v drv v dc c out c drv np nb ns d1 v in v in r z z d1 6.3v c in r s cs ndrv max17596 max17597 ldo q 1 drv d2 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
16 trip level (v cs-peak ) of 300mv. use the following equa - tion to calculate the value of r cs : cs mosfet 300mv r i = i where i mosfet is the peak current flowing through the mosfet. the devices implement 65ns of leading-edge blank - ing to ignore leading-edge current spikes. use a small rc network for additional filtering of the lead - ing edge spike on the sense waveform when need - ed. set the corner frequency between 10mhz and 20mhz. after the leading-edge blanking time, the device monitors v cs . the switching cycle is termi - nated within 30ns from v cs exceeding 300mv. the devices offer a runaway current limit scheme that protects the devices under high-input-voltage short- circuit conditions when there is insufficient output volt - age available to restore inductor current built up during the on period of the flyback/boost converter. either eight consecutive occurrences of the peak-current-limit event or one occurrence of the runaway current limit trigger a hiccup mode that protects the converter by immediately suspending switching for a period of time (t rstart ). this allows the overload current to decay due to power loss in the converter resistances, load, and the output diode of the flyback /boost converter before soft-start is attempted again. the runaway current limit is set at a v cs-peak of 360mv (typ). the peak-current-limit- triggered hiccup operation is disabled until the end of the soft-start period, while the runaway current-limit- triggered hiccup operation is always enabled. programming slope compensation (slope) the max17595/max1759 6 operate at a maximum duty cycle of 49%. in theory, they do not require slope compensation to prevent subharmonic instability that occurs naturally in continuous-conduction mode (ccm) peak-current-mode-controlled converters operating at duty cycles greater than 50%. in practice, the max17595/ max17596 require a minimum amount of slope compen - sation to provide stable operation. the devices allow the user to program this default value of slope compensation simply by leaving the slope pin unconnected. it is rec - ommended that discontinuous-mode designs also use this minimum amount of slope compensation to provide better noise immunity and jitte r-free operation. the max17597 flyback /boost converter can be designed to operate in either discontinuous-conduction mode (dcm) or to enter into continuous-conduction mode at a specific load condition for a given dc input voltage. in continuous-conduction mode, the flyback/ boost converter needs slope compensation to avoid subharmonic instability that occurs naturally over all specified load and line conditions in peak-current-mode- controlled converters operating at duty cycles greater than 50%. a minimum amount of slope signal is added to the sensed current signal even for converters operating below 50% duty to provide stable, jitter-free operation. the slope pin allows the user to program the necessary slope compensation by setting the value of the resistor (r slope ) connected from the slope pin to ground. e slope s8 rk 1.55 ? = i where the slope (s e ) is expressed in mv/ f s. frequency dithering for spread-spectrum applications (low emi) the switching frequency of the converter can be dithered in a range of q 10% by connecting a capacitor from dither/sync to sgnd, and a resistor from dither to rt as shown in the typical operating circuits . this results in lower emi. a current source at dither/sync charges capacitor c dither to 2v at 50 f a. upon reaching this trip point, it discharges c dither to 0.4v at 50 f a. the charging and discharging of the capacitor generates a triangular wave - form on dither/sync with peak levels at 0.4v and 2v and a frequency that is equal to: = tri dither 50 a f c 3.2v f figure 7. programming output voltage fb r u r b v out max17595 max17596 max17597 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
17 typically, f tri should be set close to 1khz. resistor r dither connected from dither/sync to rt deter - mines the amount of dither as follows: rt dither r % dither r = where %dither is the amount of dither expressed as a percentage of the switching frequency. setting r dither to 10 x r rt generates q 10% dither. synchronization (sync) the internal oscillator can be synchronized to an exter - nal clock by applying the clock to the dither/sync pin directly. the external clock frequency can be set any - where between 1.1x and 1.8x times the programmable switching frequency for the max17595/max17596. the synchronization feature is not available in the max17597. an external clock increases the maximum duty cycle by a factor of (f sync / f sw ). error amplifier and loop compensation the max17595/max17596/max17597 include an inter - nal transconductance error amplifier. the noninverting input of the error amplifier is internally connected to the internal reference and the inverting input is brought out at the fb pin to apply the feedback signal. the internal reference is linearly ramped up from 0v to 1.21v (typ) when the device is enabled at turn-on. after soft-start, the internal reference is connected to the bandgap. in isolated applications, where an optocoupler is used to transmit the control signal from the secondary side, the emitter current of the optocoupler flows through a resis - tor to ground to set up the feedback voltage. a shunt regulator is usually employed as a secondary-side error amplifier to drive the optocoupler photodiode to couple the control signal to the primary. the loop compensation is applied in the secondary side as an r-c network on the shunt regulator. the max17595/max17596/max17597 error amp can be set up as a proportional gain ampli - fier, or used to implement additional poles or zeros. the typical application circuits for the max17595/ max17596 use the internal error amplifier as a propor - tional gain amplifier. in nonisolated applications, the output voltage is divided down with a voltage-divider to ground and is applied to the fb pin. loop compensation is applied at the comp pin as an r-c network from comp to gnd that imple - ments the required poles and zeros, as shown in figure 8. the boost converter application circuit of figure 11 for the max17597 uses this approach. layout, grounding and bypassing all connections carrying pulsed currents must be very short and as wide as possible. the inductance of these connections must be kept to an absolute minimum due to the high di/dt of the currents in high-frequency-switching power converters. this implies that the loop areas for forward and return pulsed currents in various parts of the circuit should be minimized. additionally, small current loop areas reduce radiated emi. similarly, the heatsink of the mosfet presents a dv/dt source; therefore, the surface area of the mosfet heatsink should be minimized as much as possible. ground planes must be kept as intact as possible. the ground plane for the power section of the converter should be kept separate from the analog ground plane, except for a connection at the least noisy section of the power ground plane, typically the return of the input filter capacitor. the negative terminal of the filter capacitor, the ground return of the power switch and current-sensing resistor, must be close together. pcb layout also affects the thermal performance of the design. a number of thermal vias that connect to a large ground plane should be provided under the exposed pad of the part for efficient heat dissipation. for a sample layout that ensures first-pass success, refer to the max17595 evalu - ation kit layout available at www.maximintegrated.com . for universal ac input designs, follow all applicable safety regulations. offline power supplies can require ul, vde, and other similar agency approvals. figure 8. error-amplifier compensation network comp r z c z c p max17595 max17596 max17597 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
18 typical operating circuits figure 9. max17595 typical application circuit (universal offline isolated power supply) n1 v in 1 2 r26 4.99ki r28 2.49ki r29 221i r22 470i c8 1f c11 1000pf r21 0.2i r20 100i v fb v drv in v out c17 68nf sgnd u3 ep sgnd sgnd sgnd sgnd max17595 sgnd pgnd c21 470nf r4 549ki r3 549ki r2 549ki r1 10i ac1 ac2 c1 0.1f/ 275v ac r5 19.8ki r6 4.99ki r12 49.9ki v fb v in comp sgnd dither / sync r14 402ki r15 402ki r16 402ki c7 100nf c5 100f 450v c9 4.7f 50v c10 3300pf r18 100ki l1 6.6mh d1 c6 0.47f r19 10i pgnd pgnd pgnd v in in v out v out gnd0 t1 d2 d3 d4 c13 22f c14 22f c15 22f c16 22f r9 82.5ki rt slope ndrv pgnd pgnd sgnd cs v drv ss fb en / uvlo ovi c4 56pf r13 22ki 15v, 1.5a sgnd max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
19 typical operating circuits (continued) figure 10. max17596 typical application circuit (power supply for dc-dc applications) n1 r8 100i r9 50mi r14 8.6ki r16 16.5ki r15 8.6ki r12 10ki r17 470i r13 470i c14 0.1f v fb v drv v out c6 300pf c15 22nf c12 500nf gnd0 c16 56pf u2 u3 ndrv ep v in ss slope fb comp pgnd c5 100nf c3 0.22f c2 4.7f 50v c1 47f 63v pgnd v in v out gnd0 24v, 1.5a output 18v to 36v r7 10ki r6 20ki r5 348ki r4 49.9ki r3 22ki r1 750i c4 0.1f, 50v c9 10f 50v c11 10f 50v c12 10f 50v d1 v fb en / uvlo ovi v in v in r10 28.5ki rt sgnd cs dither/ sync max17596 u1 c10 10f 50v c13 10f 50v pgnd sgnd sgnd c7 1f v drv v drv c8 100nf d2 t1 v out max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
20 typical operating circuits (continued) figure 11. max17597 typical application circuit (nonsynchronous boost converter) ep v in l1 6.8h c9 4.7f / 50v n1 r8 100i r4 1.96ki r3 187ki r2 9.92ki r1 32.4ki r10 21ki r7 18ki r6 18ki r5 187ki r9 65mi c8 300pf v out 24v, 1a v out d1 ndrv cs rt dither sgnd sgnd pgnd ovi en / uvlo pgnd comp fb slope v drv v in ss c6 330pf c5 33nf c4 1f c3 47nf pgnd 8v to 14v dc v in v in c7 10f c1 22f v in max17597 c2 1f c10 4.7f / 50v c11 4.7f / 50v c12 10nf max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
21 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information/selector guide + denotes a lead(pb)-free/rohs-compliant package. * exposed pad. package type package code outline no. land pattern no. 16 tqfn t1633+4 21-0136 90-0032 part temp range pin package functionality uvlo, v in clamp d max max17595 ate+ -40 n c to +125 n c 16 tqfn-ep* offline flyback controller 20v, yes 46% max17596 ate+ -40 n c to +125 n c 16 tqfn-ep* low-voltage dc-dc flyback controller 4v, no 46% max17597 ate+ -40 n c to +125 n c 16 tqfn-ep* boost controller 4v, no 93% max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 22 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/12 initial release 1 2/13 updated general description , electrical characteristics tables, typical operating characteristics ; detailed description , figures 1, 3C6 ; typical operating circuits , deleted sections relating to soft-stop, flyback, and boost. 1C22 max17595/max17596/max17597 peak-current-mode controllers for flyback and boost regulators

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